The data communication system according to claim 1 wherein said network memory and said main memory comprise a data memory and a control unit which directs address generators to move data to two locations simultaneously and in parallel, one of said locations being the checksum calculating means having the at least one partial adder, and the other one being selected from one of either said network memory or said main memory the direction of said selection being dependent on the direction of data flow.Ĥ. The data communication system according to claim 1 wherein said checksum calculating means complies with a protocol checksum algorithm.ģ. Means of calculating values from the checksum calculation results and placing these values into the data packets.Ģ. A data communication system interactive so as to facilitate a flow of data between at least a main memory and network memory, said data communication system comprising:Īn adder unit having at least one partial adder for calculating checksum values and inputs,Ī checksum calculating means comprises an n-bit data byte delivery means to deliver a series of n-bit data bytes (which is called "checksum calculation results"), derived from input data, to the inputs of said adder unit, and a first direct memory accessing address generator connected to the main memory and a second direct memory accessing address generator connected to the network memory to move data in a form of data packets, each data packet having a first plurality of bytes which specify protocol information, a second plurality of bytes which specify checksum information and a third plurality of bytes which specify a block of data, to flow in one of either of two directions: from the network memory to main memory and simultaneously to checksum calculating means, orĪlternatively, from main memory to network memory and simultaneously to said checksum calculating means and Parallel adder using majority decision elementsġ. PARTIAL MODIFICATION AND CHECK SUM ACCUMULATION FOR ERROR DETECTION IN DATA SYSTEMS System for recovering data stored in failed memory unit Method for checking data written into buffered write-read memories in numerically controlled machine tools Method and an arrangement for supervising faults when transmitting data between computers ![]() Read error occurrence detector for error checking and correcting system ![]() Parity and syndrome generation for error detection and correction in digital communication systems Input/output device for programmable controller Semiconductor memory device with parallel addressing and data-correcting functions Adder control method and adder control circuitįault tolerant signal processing machine and methodįour-to-two adder cell for parallel multiplication
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